CPSC 220, Fall 2012
About the Final Exam

The final exam for CPSC 220 will be given during the official time period scheduled by the registrar: Thursday, December 13, at 7:00 PM. The exam will be held in our regular classroom, Gulick 206A.

The final exam counts for 20% of the course grade. The exam will be about six pages long. The entire final page will be a long essay that asks you to show what you've learned about how computers are constructed and how they work. The exam covers material from the entire course, with some emphasis on material that was covered since the second test. You will be given a copy of the same sheet of Larc assembly and machine language instructions that you had for the first two tests. If it is needed, you will be given a table of Larc I/O device registers.

Some things that we have covered since the second test:

writing a Larc assembler:
    generating machine language instructions for basic assembly instructions
    generating code for data directives .ascizz, .space, and .word
    determining label addresses
    why several passes through the program are necessary
    dealing with large immediates and long branches
the memory hierarchy:
     on-chip memory; RAM; hard disk (or solid-state drive)
the general idea of caching (such as web caches)
memory caches
multilevel caches
why caching works:  locality
temporal locality
spacial locality
cache hits and cache misses
direct-mapped cache (each memory block has only one possible cache location)
structure of direct-mapped cache:
      three-part memory address for a location in memory,  xxxyyyzzz
      xxxyyy is the block number in memory
      zzz is the offset of the location within the block
      yyy is the corresponding block number in the cache
      xxx is a "tag" that tells which memory block is currently in the cache block
      each cache block also has a "valid" bit to tell whether it is empty
fully associative cache (a memory block can be put into any cache block)
handling writes to memory
      write-through cache
handling I/O
I/O devices such as:  keyboard, mouse, monitor, disk drive, network
north bridge switch connects processor to RAM and I/O bus
south bridge or I/O bus connects to north bridge and to I/O devices
device driver: software for communicating with and controlling a device
memory-mapped I/O
device control registers
interrupt handler
context switch
how does the CPU respond to an interrupt?
interrupt priorities and masking of interrupts
DMA (direct memory access)

writing a Larc I/O trap handler:
   using the device control registers (KCR, KDR, MDR, MCR)
   polling the KCR or MCR to test whether the device is ready
   using KDR/MDR to read/write a character
   kernel mode versus user mode
   the meaning of the MEM_BASE and MEM_LIMIT device registers
   using sysretn to return from the trap
   storing 1 into PCR to halt the system

multiplying binary numbers
implementing multiplication in hardware
dividing binary numbers

floating point numbers:
     sign bit / fraction / exponent
     "bias" representation for exponent value
     the 32-bit floating point format: 
         sign bit,  8 exponent bits, 23 fraction bits, bias = 127
     special values:  0, -0, infinity, minus infinity, NaN
         zero:      0 00000000 00000000000000000000000
         -zero:     1 00000000 00000000000000000000000
         infinity:  0 11111111 00000000000000000000000
         -infinity: 1 11111111 00000000000000000000000
         NaN:       ? 11111111 ---anything non-zero---

     regular numbers: (-1)sign * 1.fraction * 2exponent - bias
         where exponent is between 1 to 254 (00000001 to 11111110), inclusive
     denormalized numbers: (-1)sign * 0.fraction * 2-127
         where exponent is 0

Here are some important ideas from earlier in the semester:

Java bitwise logical operators
Java shift operators
using logical and shift operators to manipulate bits in a number

switches as the fundamental building blocks of computers
relays, vacuum tubes, transistors

binary numbers and hexadecimal numbers
twos-complement representation of binary numbers

logic gates
building circuits from logic gates
basic combinational circuits:  adder, multiplexor, decoder, ALU
memory circuits
register file
program counter register
control circuits
the role of the clock in a computer

machine language
assembly language
ISA (instruction set architecture)
basic structure of the Larc model computer
programming in the Larc assembly language
how high-level language constructs translate into assembly language
subroutines, activation records, and the stack
saving and restoring registers on the stack

MIPS; comparing MIPS to Larc
the basic data path in Larc or MIPS
pipelined data paths
hazards and pipeline stalls