CPSC 220, Fall 2012
About the Second Test

The second test in CS 220 will be given in class on Friday, November 2. It will be on material that we have covered since the first test, although you will also need to know earlier material to the extent that it is a prerequisite for previous material. In particular, you still need to know all about Larc assembly language. Major topics include assembly language programming for Larc, using the stack to implement subroutines in assembly language, MIPS and other architectures, memory circuits, how Larc can be implemented in hardware, and the basic ideas of pipelining. Readings include Sections 2.5 through 2.10 and 4.1 through 4.5 in the textbook.

The format of the test will be as usual. There will be four pages. The types of questions might include: definitions, short-answer and longer essay-type questions, coding questions (using Larc assembly language), reading and interpreting code, designing circuits, and explaining what a given circuit does.

You will be provided with tables of Larc registers and assembly language instructions.

Here are some terms and ideas that you should be familiar with:

the stack and the stack pointer register, $sp, in Larc
using the stack to implement subroutines
activation records
creating and destroying activation records on the stack
saving the return address on the stack
saving "spilled" registers on the stack
calling a subroutine; the jal instruction in Larc assembly language
returning from a subroutine; the jr instruction in Larc assembly language

MIPS assembly language
   32-bit instructions
   32 registers in the register file
   byte-addressable memory, and why PC goes up by 4 instead of by 1
   support for bytes and half-words as well as words in memory store/load instructions
   support for unsigned numbers
comparisons with Larc
accumulator architectures
format of assembly language instructions for accumulator architectures, such as "ADD 17"

combinatorial logic circuit
feedback loops in logic circuits
sequential logic circuit
memory circuits
Set/Reset Latch
D Latch
the clock and its role in a computer
memory circuits that "trigger" on the rising or falling clock edge
building a register from flip-flops

the Larc register file (inputs and outputs and how it can be constructed)
the Larc ALU and how it can be 
                 constructed from components that do arithmetic operations
the Larc PC and how its input is computed
the idea of the data path in Larc and MIPS
control wires and control circuits
how control circuits are designed, based on machine language opcodes
how clock inputs are used in Larc components
how multiplexors are used in the Larc simulation

pipelined CPU architectures
pipeline stages
how pipelining speeds up computation
MIPS pipeline stages:  
        Instruction fetch, instruction decode, execute, memory access, writeback
pipeline registers and what they are used for
pipeline stalls (also known as bubbles, implemented as "no-ops")
how hazards can be avoided or dealt with
pipeline hazards
data hazards; recognizing data hazards in assembly language instructions
control hazards; speculative execution