The Larc infrastructure is for use in teaching computer architecture. Larc stands for Little ARChitecture and is an ISA and assembly language defined specifically for use in the classroom. The Larc project includes a functional simulator, an assembler, a machine language and assembly language debugger, and a Java-like compiler (Bantam Java) and C-like compiler that both target Larc (the compilers are only available via instructor request). The infrastructure includes documentation, assignments, and code, for both students and instructors, which are linked below.

This project can be integrated with both the Bantam Java Compiler Project and the VIREOS Operating Systems Project. The Bantam Java compiler can target Larc and allow students in an upper-level compiler course to make use of the Larc ISA they used in introductory architecture. The VIREOS operating system can run on Larc and allow students in an upper-level operating systems course to build on top of an ISA they are already familiar with. Some of this integration has been at Hobart and William Smith Colleges with some success. At the same time, Larc is a stand-alone project and can be used without incorporating Bantam Java and VIREOS into the curriculum.

Questions. If you have any questions or suggestions, please send email to the contact address at the bottom of the page.

Toolset:
Project code:
      Larc project toolset (compressed tarball)

Documentation:
      Lab manual
      API for Java labs
      CCSCNE paper (pdf)
      CCSCNE presentation: 1-up pdf, 4-up pdf, ppt
      README with changes made in latest version

Solution code:
Send email to the contact address at the bottom of the page (expect some delay as each request must be validated).

Compilers:
For a Java-like compiler (Bantam Java) or C-like compiler targeting Larc, send email to the contact address listed below (expect some delay as each request must be validated).

Previous versions:
      Version 1.0

Staff:
      Marc Corliss -- Hobart and William Smith Colleges

Several undergraduate students have also worked on components of this infrastructure:
      Rob Hendry -- Hobart and William Smith Colleges -- Summer 2007
                           Helped design initial ISA, implemented an assembler, and functional and timing simulators
                           (now a PhD candidate in Electrical Engineering at Columbia University)
      Marcela Melara -- Hobart and William Smith Colleges -- Summer 2010
                                Wrote synthesizable processor specification, configured an Altera DE1 FPGA

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Contact: corliss at hws dot edu
Last modified: Mon Mar 14 08:30:16 EDT 2011