CPSC220: Introduction to Computer Architecture (Fall 2013)

Assignment #9

Due at the start of class on Friday, 12/06/2013

Reading and Tools

Over the past few weeks, we have studied the construction of a simple one-instruction-per-cycle datapath for a subset of the MIPS ISA. In the last assignment, you implemented first passes at two two subcomponents of this data path, program storage and instruction selection (with the problems of branch and jump target computation deferred) and support for MIPS's three-address format (R-type) arithmetic and logical operations. In this assignment, you will complete this simulation

Your job

Implement a complete datapath that supports the following MIPS instructions: add, sub, and, or, slt, lw, sw, beq, and j. Figure 4.24 of Patterson and Hennessy gives an outline of the necessary structure, of course. Although we have identified suitable abstractions for several subcomponents—instruction storage and selection, branch/jump computation, and basic R-type operations—many of the other details remain open. You may solve them as you like, subject to the requirement that you offer the following rough decomposition into subcomponents:

  1. An instruction selection unit. This is the abstraction we completed in class on 11/20. In addition to the clock signal, it should take as input the Jump and Branch signals from the Control unit (see below) and the Zero output from the Arithmetic/Logic subcomponent. On each clock cycle, it should output the next instruction to be executed. All computation of the next instruction to execute (sequence, branches, and unconditional jumps) should be handled inside the component.

  2. The R-type instructions. Refine your arithmetic/logic subcomponent from Assignment 8 to support appropriate inputs from the instruction selection unit, the control unit, and the data memory unit.

  3. Control unit. This unit should take as input the upper six bits of each instruction (i.e. the opcode) and output a set of 1-bit signals, per the discussion given in section 4.4 of P&H.

  4. Data memory unit. Provide an abstraction of the components necessary to support the lw and sw operations, so that data is correctly read and written between the registers (in the arithmetic/logic component) and a RAM.

    NOTE: Don't forget that a RAM component in Logisim is only 24-bit addressable, and only by word, not by byte. You should feel free to use the "32/24" hack from my Instruction selection solution.

To hand in your files: