Some Notes

We have discussed the Larc simulation extensively in class, and I will not repeat the discussion here. (You have the hand-drawn diagram, simular to what I put on the board in class, as a starting point.) But here are some notes about LogiSim and the simulation:

• Use the LogiSim documentation, available in the "Help" menu, to understand how LogiSim and its built-in components work. The "Library Reference" has complete documentation about each individual component.
• You can keep your work in several .circ files. One of them will be the main file, which defines the full Larc simulation. The other files can contain subcomponents that are used in the simulation. To add the circuits from a file to your main project file, use the command "Project" / "Load Library" / "Logisim Library". The file will be added to the list of component folders in the upper left section fo the window, and all the circuits from the file will be listed and available for use. I used four extra files in my version, to hold the ALU, the registers, various utility circuits, and control circuits. The picture at the right shows the resulting component list in the LogiSim window, with util opened to show the individual circuits that it contains.
• You can use a ROM component to represent the instruction memory. A ROM is very simple, with just an address input and a data output. You should set the number of bits for both address and data to 16. To set the contents of the ROM, right-click and select "Edit". This will allow you to enter values into the entire memory. You can also load the contents from a file.
• You can use a RAM component for the data memory. Set the number of data and address bits to 16. Set its "Data Interface" to "Separate Load and Store Ports." (I don't fully understand the other modes.) You will need to use the clock input. You might want to attach an input to "clr", which will allow you to reset the memory contents to zero. You might find it useful to do that for testing purposes.
• A register in LogiSim has separate inputs for the clock and for enabling writing. So, when using LogiSim registers, the wiring of the register file won't be exactly the same as the version we did in class.
• Memory components in LogiSim are set to "trigger" on the rising clock edge by default. We used the falling clock edge in class. However, it really doesn't make a difference, and I used rising clock edge in my own Larc simulation.
• You should treat any syscall as a halt command. You can implement it by stopping the clock. (Feed a "stop-clock" wire together with the clock output, through an AND gate to get the clock signal that you send to all the components, so the components don't see the clock tick when stop-clock is enabled.)
• Note that you can "poke" a clock component, to turn it on and off by hand. Note that you can "poke" any wire in the circuit to see what value it is carrying. This will be essential for debugging your work, since you can step though a program and check that all the input and output wires are carrying the values that you expect.
• The hard parts of the project are designing the control circuits and wiring everything together correctly in the full Larc simulation. I suggest that your group work together on analyzing the control problem and designing the control circuits. For the other sub-components, you might be able to divide up the work so that you can do some work individually. However, the organization is all up to you. In any case, you should keep all your files in your common group folder in /classes/cs220/larc-in-logisim.
• I might have some more notes next week, after seeing how things go during the first week.

Before next week's lab, I expect all the basic circuits and at least some of the control circuits to be ready, and the main project file to be started. You should be prepared to show me your work at the start of next week's lab.